WHO I AM
Email me
Connect
Tweet me
Where is Dave?
Intel : Root caused a blocking memory aliasing issue by creating a C model memory subsystem simulation using multiple memory configurations, reducing debugging time by 136%. Primary engineer, successfully participating in launching PCI-Express. Exercised PCI Host Interface blocks on a FPGA by writing Window drivers and test applications in C, identifying three missing interrupts increasing the throughput of the block by 35%.
PAST & PRESENT
Dell : Developed embedded Linux C based applications for remote update and RAID management coordinated with a team based in India. Designed a working prototype detecting memory leaks, reducing debugging time by 300%.
![](https://static.wixstatic.com/media/d990ec_96cbf4672c7b423b91c201e944d96be2~mv2.png/v1/fill/w_101,h_100,al_c,q_85,usm_0.66_1.00_0.01,enc_auto/d990ec_96cbf4672c7b423b91c201e944d96be2~mv2.png)
![](https://static.wixstatic.com/media/d990ec_14d7d0ba5f984dc3ba0708d42a83ba2f~mv2.png/v1/fill/w_95,h_59,al_c,q_85,usm_0.66_1.00_0.01,enc_auto/d990ec_14d7d0ba5f984dc3ba0708d42a83ba2f~mv2.png)
![](https://static.wixstatic.com/media/d990ec_8c252943f855469ea4c7ae58230ee3cd~mv2.png/v1/fill/w_160,h_38,al_c,q_85,usm_0.66_1.00_0.01,enc_auto/d990ec_8c252943f855469ea4c7ae58230ee3cd~mv2.png)
Advanced Micro Devices : Group redesigned a Graphic Processing Unit for performance and reduced power. Validated EEC functionality for an HPC GPU implementation.
Call me
Austin, Texas
Senior technical lead for firmware, software, and hardware projects driving solutions for multiple industries ranging from video imaging to server platforms; accustomed to working with dispersed geographies. Participated in all phases of development including simulation, emulation, and power-on. Well known for creating maintainable solutions in response to unresolved low-level memory failures. Broad experience in writing Windows and Linux drivers for essential tools supporting new technologies and driving FPGA implementations. Experienced in updating GPU RTL to support smaller form factors for several systems on a chip (SOC) designs.
Text me